FIG. 1 is a block diagram of a conventional disk-drive read channel 10, which includes a read path 12 and an gain-control circuit 14. The read path 12 includes a disk 16 for storing data, a read head 18 for reading data from the disk 16 and for generating a corresponding read signal, a signal-controlled amplifier 20 for amplifying the read signal, an analog-to-digital (AND) converter 22 for sampling and digitizing the amplified read signal, a finite-impulse-response (FIR) filter 24 for equalizing the digital samples, and a Viterbi detector 26 for recovering the read data from the equalized samples. Although shown having a single A/D converter 22, the read path 12 may include two or more parallel A/D converters as is well known. The gain-control circuit 14 includes a gain-determination circuit 28 for generating a digital gain-control signal, and a digital-to-analog converter (D/A) 30 for converting the digital gain-control signal into an analog gain-control signal (voltage or current).
FIG. 2 is a diagram of a preamble sinusoid generated by the amplifier 20 of FIG. 1 and having a peak amplitude A. A preamble is a bit pattern that is stored at the beginning of each data sector (not shown) of the disk 16. This bit pattern is designed such that while the read head 18 reads the preamble, the read signal from the head 18 and the amplified read signal from the amplifier 20 are sinusoids or approximate sinusoids. As discussed below, the read channel 10 uses the preamble to calibrate itself in preparation of the head 18 reading the data that follows the preamble. Because the preamble occupies storage locations that could otherwise store data, one usually desires the preamble to be as short as possible. But if the preamble is too short, then the read channel 10 may calibrate itself improperly, and thus may read the stored data inaccurately. Therefore, the calibration time of the read channel 10 typically dictates the minimum length of the preamble.
Referring to FIGS. 1 and 2, the gain-control circuit 14 uses equalized samples of the preamble sinusoid from the FIR filter 24 to calibrate the gain of the amplifier 20. The Viterbi detector 26 is designed to process samples that are within a predetermined range of values, this range including a predetermined maximum value and a predetermined minimum value. Furthermore, the FIR samples of the preamble-sinusoid's positive and negative peaks respectively correspond to maximum and minimum sample values. Therefore, while the head 18 reads the preamble, the gain-control circuit 14 uses feedback—the amplifier 20, A/D 22, FIR 24 and control circuit 14 form a feedback loop—to adjust the gain of the amplifier 20 so that at the output of the FIR 24, the positive-peak and negative-peak samples equal the predetermined maximum and minimum values, respectively, before the head 18 begins reading data.
Unfortunately, the gain-control circuit 14 often limits the storage density of the disk 16. To insure that the gain-adjust feedback loop is stable and can finely tune the gain of the amplifier 20, the circuit 14 typically has a relatively long time constant, i.e., operates relatively slowly. Therefore, the circuit 14 often must process a relatively large number of preamble-peak samples from the FIR 24 before the gain of the amplifier 20 settles to an acceptable level. Consequently, the circuit 14 requires the disk 16 to store a relatively long preamble in each data sector to insure that the amplifier gain settles to an acceptable level before the read head 18 begins reading the data that follows the preamble. Unfortunately, this requirement limits the number of data bits that each data sector can store, and thus limits the total number of data bits that the disk 16 can store.